An advanced extensible interface (AXI, Advanced eXtensible Interface) is a high performance system bus for interconnecting high-speed deep sub-micron integrated circuits. FIG. 1a illustrates an AXI protocol architecture, in which the AXI transmission is based on five transmission channels. From the perspective of an upper layer protocol, the AXI divides the transmission into five packets (Packet) by directions, namely, address read (AR, Address Read), read data (R, Read), address write (AW, Address Write), write data (W, Write), and write response (B, Back). The AR packet, AW packet, and W packet are sent to the slave device (Slave) by the master device (Master), and the R packet and B packet are returned to the master device by the slave device. A typical read operation of the AXI consists of one AR and several Rs, and a typical write operation of the AXI consists of one AW, several Ws, and one B. One transmission consists of multiple packets marked with the same device identity (ID, IDentity). Each packet is highly independent of each other and has no fixed phase relationship. Therefore, an efficient outstanding transmission is supported, that is, the master device or the slave device may have several active (Active) yet incomplete operations, and control the sequence of these operations according to the ID.
The AXI bus is also built into various complex on-chip bus structures in addition to the point-to-point connection between the master device and the slave device, including such topologies as shared bus (Shared Bus) and full cross-connect bus (Crossbar), to implement on-chip interconnections between multiple master devices and multiple slave devices.
FIG. 1b is a schematic diagram of a crossbar fabric in the prior art. As shown in FIG. 1b, each master device has a connection relationship with all the slave devices. Therefore, so long as multiple crosspoints (Crosspoint) are closed at the same time, data can be transmitted between multiple different master devices and slave devices at the same time, so that all ports can switch data at a line speed. The quantity of AXI bus signal lines is the product of the quantity of signal lines connected to the AXI, the quantity of master interfaces, and the quantity of slave interfaces. When the quantity of ports is increased linearly, the quantity of signal lines is squared. However, the multi-channel characteristics of the AXI bus determine that a large number of signal lines (about 300 pieces) are included in a group of signal lines. Therefore, a 3×3 crossbar fabric includes a total of 2,700 AXI signal lines, while a 4×4 crossbar fabric includes 4,800 AXI signal lines.
In the process of researching and practicing the prior art, the inventor of the present invention discovers that the prior art has the following problem: In a scenario where a lot of master devices and slave devices are available, if the AXI bus is built using the crossbar fabric in the prior art, the number of signal lines is huge. Therefore, the wiring is hard to implement on the chip or even if the wiring can be implemented, the signal lines are very long, which causes a longer latency, greatly reduces the bus frequency, and therefore affects the bus performance. In addition, the AXI bus built using the crossbar fabric is very difficult to access and extend. Furthermore, the routing mechanism adopts a single routing structure, which easily causes routing congestion.